In semi-conductor components, e.g. memory components such as DRAMs (DRAM=Dynamic Random Access Memory and/or dynamic read/write memory) based on CMOS technology, so-called clock signals are used for the chronological co-ordination of the processing and/or relaying of data.
Conventional semi-conductor components use a “single-ended” clock signal CLK, present on a single line, for this purpose.
The data may then for instance be processed/relayed at respective rising edges of the single-ended clock signal (or alternatively at respective falling edges of the single-ended clock signal).
Further, so-called DDR components, e.g. DDR-DRAMs (DDR-DRAM=double data rate DRAM and/or DRAM with a double data rate) are already well known.
In DDR-DRAMs—instead of one “single ended” clock signal CLK—two differential, inverse clock signals CLK and BCLK present on two separate lines are used.
Every time, for instance, when the first of the two clock signals changes e.g. from a logic “high” state (e.g. a high voltage level) to e.g. a logic “low” state (e.g. a low voltage level), the second clock signal—essentially simultaneously—changes its state from logic “low” to logic “high” (e.g. from a low to a high voltage level).
Conversely, whenever the first clock signal changes from a logic “low” state (e.g. from a low voltage level) to a logic “high” state (e.g. a high voltage level), the second clock signal (again essentially simultaneously) changes its state from logic “high” to logic “low” (e.g. from a high to a low voltage level).
With DDR-DRAMs, data may be processed/relayed both at respective rising, and at respective falling edges of the clock signals.
This means that data is processed/relayed more frequently and/or faster (more particularly, twice as frequently and/or twice as fast) with a DDR-DRAM using differential, inverse clock signals, than with a corresponding conventional DRAM using a “single ended” clock signal; in other words the data rate of DDR-DRAMs is twice as high as that of corresponding DRAMs.
In conventional systems, the respective single ended clock signal CLK (or the respective differential clock signals CLK, BCLK) are generated by a respective—external—clock generating device, and transmitted to the respective semi-conductor component(s), e.g. a DRAM, a DDR-DRAM, etc.
The respective component comprises a means, e.g. a respective DLL-circuit (DLL=Delay Locked Loop), for generating the respective—internal—clock signal(s) DQS (or DQS/BDQS) (“data strobe” signal(s)) out of the—external—clock signal(s) CLK (or CLK/BCLK) provided by the external clock generating device.
The—internally used—DQS- (or DQS-/BDQS-) signal(s) need to be synchronized with the—external—CLK- (or CLK-/BCLK-) signal(s), e.g., the falling and rising edges of the DQS- (or DQS-/BDQS-) signal(s) provided by the DLL-circuit should e.g. occur at the same time as respective falling and rising edges of the CLK- (or CLK-/BCLK-) signal(s) provided by the external clock generating device.
Problems might arise if—due to distortions—e.g. the time Th the CLK signal—when received by the respective component, e.g. DRAM/DDR-DRAM—is logic “high” (and the BCLK signal is logic “low”) is longer than the time T1 the CLk signal is logic “low” (and the BCLK signal is logic “high”), or the other way round (“clock distortion”).